At some point in semiconductor wafer processing, it becomes necessary to make conductive connections to exposed electrically conductive areas on a semiconductor wafer, such as active electronic device areas and interconnecting lines. Typically, interconnecting lines need to be formed elevationally above such areas to extend to other parts of the circuitry or to larger bonding pads to provide interconnect points for the finished die.
Throughout the evolution of integrated circuits, the aim of device scaling has been twofold: (1) to increase circuit performance (mainly by increasing circuit speed), and (2) to increase the functional complexity of the circuits. At the outset, scaling down of active device sizes was a very effective means of achieving these goals. Eventually, the scaling of active devices became less profitable, as the limitations of the circuit speed and maximum functional density came to depend more on the characteristics of the interconnects than on the scaled devices. In addition, the aspects of silicon utilization, chip cost, and ease and flexibility of integrated circuit design were also adversely affected by interconnect-technology restrictions.
The approaches to lifting these limitations have predominantly involved the implementation of multilevel-interconnect schemes. The typical method for forming these perpendicular conductive paths between metal levels and establishing contact with underlying areas of conductive interconnect lines or active device areas about wafers and dies has employed the step of first applying a thick layer of insulating material, such as SiO.sub.2. A layer of photoresist is then applied to the insulating layer and selectively exposed and developed. Next, the wafer is etched to define vertical contact holes extending to selected active areas or interconnecting lines.
Deposition of a metal layer and subsequent etching results in a Metal layer that includes a first level of conduction strips and perpendicular contacts leading to selected active areas and/or interconnecting conductors.
After application of an interlevel dielectric layer, the process is repeated to form an additional Metal layer. Additional levels of dielectric and metal can be added to complete the metallization process.
Because perpendicular interconnecting posts or studs are required between spaced metal levels in multilevel interconnect structures, three metal depositions must usually occur--the first forms contacts to the underlying electrically conductive areas, such as active electronic device areas, and a first level of conduction strips about the wafer; the second forms the required posts, and the third forms the conduction strips of the next metal level.
Where tungsten is employed as the first level metal, the first two applications of metal involve deposition of tungsten, which is typically a very expensive process. The present method negates the need for the second deposition of tungsten, using instead the first metal deposition (which can be accomplished by an suitable metallurgical process) to form pillars extending outward from the first metal level.
Prior processes require substantial care to assure that good ohmic contact is established between the plugs as they are being formed and the underlying metal level. The present invention eliminates this concern by producing the plugs as integral pillars in the first level metal structure .